The invention relates to a circuit arrangement for error recognition of a two-wire data bus through which transmitted, dominant bits are differentially transmitted on the two bus lines.
In such data buses such as, for example, the CAN bus, whose properties have been laid down in ISO 11898, separate data bits are differentially transmitted on the two lines of the bus. In the rest state, both lines of the bus have approximately the same potential because both lines are coupled together via a terminating resistor. A dominant bit is actively transmitted from a transmitter to the bus by switching on a drive current. This transmission is performed differentially, i.e. the potential of one line of the bus is raised and the potential of the other line of the bus is lowered. A recessive bit is transmitted by a transmitter by switching off the drive current. Consequently, the two bus lines again approximately assume the same potential.
Errors of a different nature may occur in data buses of this type. Short-circuits of the individual lines may occur with respect to a reference potential but also with respect to each other.
Known circuit arrangements therefore evaluate the potentials of the lines and attempt to take such short-circuits into account. In a circuit arrangement which is known from U.S. Pat. No. 5,488,306, the difference between the potentials of the two bus lines is also evaluated. All of these known arrangements have the essential drawback that they react to mass offsets of the two bus lines. Such mass offsets, in which the potential of the two lines is shifted, may particularly occur in applications in the field of automobiles. In the known error recognition circuits, these mass offsets easily lead to false error messages, i.e. error messages which only refer to the mass offsets, which actually do not represent errors, and do not refer to actual short-circuits of the lines.
It is an object of the invention to provide a circuit arrangement of the type described in the opening paragraph, which allows a secure error recognition without reacting to mass offsets of the bus lines.
According to the invention, this object is solved in that the arrangement comprises means for measuring the differential current, by means of which the difference of the drive currents with which the two bus lines are driven is measured in a transmitter when transmitting dominant bits on the data bus, and in that evaluation means are provided which supply an error signal when the difference between the drive currents exceeds a predetermined limit value.
The fundamental idea of the invention is that there is no potential measurement but a current measurement. The difference between the two drive currents for driving a dominant bit on the data bus is measured. Transmitters transmitting data bits on the data bus generally have two drivers each driving a data bus line. Since the bits are differentially transmitted on the data bus, the drive currents have opposite signs. The difference between these drive currents is determined. If one of the two drive currents increased significantly, the difference would also increase significantly on the basis of the opposite polarity of the two drive currents. A predetermined limit value is provided which, in normal operation, is not exceeded by the difference between the drive currents. In one of the short-circuits described above, the differential current is, however, raised significantly and the predetermined limit value is exceeded. The circuit arrangement then supplies an error message.
Since both drive currents are measured and evaluated, potential shifts on the two lines of the two-wire bus do not lead to error messages because these potential shifts do not essentially influence the drive currents, because the terminating resistor of the two lines is arranged between them without potential.
Moreover, the circuit arrangement according to the invention has the general advantage of being tolerant to external EMV influences on the bus lines.
In accordance with an embodiment of the invention as defined in claim 2, the circuit arrangement is suitable for the CAN bus in accordance with ISO 11898, because this bus is used in vehicles in which mass offsets or EMV influences often occur in practice. Also under these conditions, the circuit arrangement according to the invention supplies an error signal only when there is actually a mutual short-circuit of the lines or when a short-circuit has occurred at a different potential.
In a further embodiment of the invention as defined in claim 3, the drive currents initially rise steeply when a transmitter transmits a dominant bit, because the lines of the bus represent a capacitive load. It is therefore advantageous not to measure and/or evaluate the difference between the drive currents at the start of a dominant bit but in the second half of the period of this bit because the transient phenomena due to the capacitive/inductive load represented by the two lines will then have declined.
In accordance with a further embodiment of the invention as defined in claim 5, the TXD signal provided in the CAN bus protocol may be advantageously evaluated for this purpose. The TXD signal indicates the period of a dominant bit. Advantageously, an orientation may be performed on the trailing edge of the TXD signal for each individual bit, because the transient phenomena on the bus lines have taken place at this instant and the drive currents are no longer influenced by the transient phenomena at this instant.
A further embodiment of the invention as defined in claim 4 ensures a very secure recognition of a short-circuit of the two lines of the data bus. To this end, the two drive currents are individually compared with a reference current, and an error message is supplied only when the two drive currents individually exceed the reference current. This results in an additional security for error recognition.
Since it is advantageous, as elucidated above, to evaluate the drive currents by the end of a bit phase of a dominant bit on the data bus, a further embodiment of the invention as defined in claim 6 is characterized in that the measurement and/or evaluation of the drive currents or the difference between the drive currents is triggered by means of a timer so that the measurement and/or evaluation is performed at a predetermined interval after the start of transmitting a dominant bit. This provides a further advantageous possibility in which the measurement of the difference between the drive currents is performed without influencing the transient phenomena on the bus lines.
The CAN protocol provides a simultaneous transmission by a plurality of CAN transceivers of dominant bits on the bus during a so-called arbitration phase as well as during transmission of the acknowledge bit and the error flex. During this phase, the current difference measurement may yield values which lead to an unwanted error indication. In a further embodiment of the invention as defined in claim 7, it is therefore advantageous to measure and/or evaluate the drive currents or their differences only during a transmit interrupt service routine in the CAN bus protocol, because in this phase only one participant may actively transmit bits on the bus. During this phase, a secure evaluation of the drive currents without interfering influences is thus possible.
To ensure that an error signal supplied by the circuit arrangement according to the invention is available for a sufficiently long time and is not destroyed by the arbitration phase of the next telegram, a further embodiment of the invention as defined in claim 8 is characterized in that the arrangement comprises shift registers by means of which the result of the evaluation is buffered so that an error signal may be supplied in a delayed manner. The length of this shift register determines the time available for a transmit interrupt service routine to evaluate an error indication.
To prevent differential currents occurring already during transmission of an individual bit from triggering an error indication, a further embodiment of the invention as defined in claim 9 is characterized in that the arrangement comprises a majority circuit. Such a majority circuit only triggers an error signal when the outcome of the majority of a plurality of measurements has shown that the limit value has been exceeded. This majority circuit can be advantageously connected to a shift register, because the shift register simultaneously supplies evaluation results for a plurality of dominant bits.
In a further embodiment of the invention as defined in claim 10, such a majority evaluation may be advantageously performed in that an error message is preferably suppressed only when the differential current has exceeded the predetermined limit value during transmission of a single bit, but not during transmission of the bits adjacent to this bit, i.e. the previous and the subsequent bit. In this case, it can be concluded that a faulty error evaluation may have taken place for the single bit. An error message is then suppressed.
A further embodiment of the invention as defined in claim 11 has for its object to exclude arbitration phases and acknowledge bits from the error evaluation by means of summation of the drive currents and thus to prevent a correctly evaluated error signal from being inadvertently overwritten prematurely during such a phase. Arbitration phases and acknowledge bits are characterized in that a plurality of transceivers can simultaneously transmit a dominant bit on the bus. Consequently, the sum of the two drive currents falls below a limit value and the current difference signal is not evaluated.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.